1. Field of the Invention
This invention relates generally to the field of digital to analog conversion. In particular, the invention relates to implementing cyclic return to zero techniques for digital to analog converters.
2. Description of Related Art
Ideally, a digital-to-analog converter (DAC) with a continuous-time output (e.g., a zero-order-hold output as opposed to a switched-capacitor output) converts an input signal, represented as a sequence of digital numbers, into an analog output waveform, represented as a time-varying voltage or current, without introducing any error. However, practical DACs introduce error consisting of random noise, linear distortion, and nonlinear distortion. The term noise is generally used to denote error that is not correlated with the DAC input signal, the term linear distortion is generally used to denote error that is linearly related to the input signal, and the term nonlinear distortion (also called harmonic distortion) is generally used to denote error that is nonlinearly related to the input signal.
In high precision DACs with continuous-time outputs, the overall DAC error is often dominated by nonlinear distortion. However, in many applications, such as high-fidelity audio systems and transmitters for wireless communications, nonlinear distortion of a given power is more problematic than noise and linear distortion of comparable power. Unfortunately, to avoid introducing nonlinear distortion it is not only necessary for the DAC output to settle to the correct output level by the end of each sample period, but the transient associated with the settling process must not contain nonlinear distortion. In many high-performance DACs with continuous-time outputs, nonlinear transient settling behavior is the dominant source of nonlinear distortion.
For example, assume x[n] represents the digital input sequence to a given DAC, and assume y(t) represents the continuous-time analog output waveform generated by the DAC in response to x[n]. Since x[n] is a discrete-time sequence, and y(t) is a continuous-time function, a DAC performs interpolation to convert the sequence of discrete numbers into a continuous-time waveform. A common type of interpolation used is zero-order-hold interpolation, which sets y(t)=xcex1x[n]+xcex2 during each sample interval, i.e., during nTxe2x89xa6t less than (n+1)T for each integer n, where xcex1 is a constant scale factor, xcex2 is a constant offset, and T is the sample period of the input sequence. In this case, during each sample interval, y(t) is held constant at a level which, neglecting the constant offset, is proportional to the corresponding discrete value of the input sequence. At the end of each sample interval, i.e., at each time (n+1)T, the output waveform abruptly jumps to the level corresponding to the next input sample value, i.e., xcex1x[n+1]+xcex2.
Since no physical device can generate a truly discontinuous waveform, zero-order-hold interpolation is an idealization; i.e. practical DACs can only approximate the zero-order-hold behavior. Therefore, a transient error waveform can be defined as the difference between the actual interpolation function implemented by the DAC and ideal zero-order-hold interpolation. In many DACs, it is also possible to define a discrete error sequence that represents errors not associated with the interpolation process such as often arise from component mismatches. Therefore, in general the output of the DAC is given by
y(t)=xcex1x[n]+xcex2+ed[n]+el(t), nTxe2x89xa6t less than (n+1)T,xe2x80x83xe2x80x83(1)
for each value of n, where ed[n] is the discrete error and el(t) is the transient error. Well known techniques such as dynamic element matching can be used to reduce nonlinear distortion contributed by the discrete error sequence of the DAC if necessary. Therefore, to simplify the presentation the discrete error sequence is ignored or assumed to be zero throughout much of the patent. To further simplify the presentation, the DAC offset, xcex2, is assumed to be zero without loss of generality.
FIG. 1 provides a comparison between representative continuous-time output waveforms from an idealized DAC with ideal zero-order-hold interpolation, and from a typical practical DAC that only approximates zero-order-hold interpolation. More particularly, FIG. 1 shows representative continuous-time DAC output waveforms: the top waveform 102 corresponds to ideal zero-order-hold interpolation, the middle waveform 104 represents the approximate zero-order-hold interpolation typically implemented by practical DACs, and the bottom waveform 106 represents the transient error between the actual and ideal interpolations. The bottom waveform 106 is the transient error associated with the practical DAC; i.e. it is the difference between the top and middle waveforms 102 and 104, respectively. As is illustrated in FIG. 1, a the transient error consists of a train of transient pulses each of which starts at the beginning of a sample period and asymptotically approaches zero. It should be noted that if the discrete error sequence were not zero, the transient pulse originating in the nth sample period would asymptotically approach ed[n]. Therefore, the transient error can be written in the form:                                                         e              t                        ⁡                          (              t              )                                =                                    ∑                              n                =                                  -                  ∞                                            ∞                        ⁢                          xe2x80x83                        ⁢                                          p                n                            ⁡                              (                                  t                  -                  nT                                )                                                    ,                            (        2        )            
Where pn(t) is the transient pulse associated with the nth sample interval. Typically, pn(t) is causal, has a peak at t=0, and has a shape that depends nonlinearly on both the (nxe2x88x921)th and nth DAC input samples.
As discussed previously, it is desirable to avoid having the transient error introduce nonlinear distortion. Therefore, it is undesirable to have a nonlinear relationship between the transient pulses and the DAC input values. In general, it is not possible to eliminate the transient pulses, but it is possible to design a DAC with transient error that consists of uniformly shaped and spaced transient pulses each of which is scaled by the corresponding input sequence sample. To the extent that this is done, nonlinear distortion is eliminated from the transient error. Two prior art methods of achieving this result will now be discussed.
Both of the prior art methods involve multiple one-bit DACs, i.e., DACs whose inputs are one-bit sequences, which are combined to yield a composite multi-bit DAC. FIG. 2 is a block diagram illustrating an exemplary composite DAC 200 comprising eight one-bit DACs 2021-2028 and summing operation 206 that can be utilized in implementing the two prior art methods. The overall DAC input, x[n], is a sequence of 4-bit numbers each of which is restricted to the set {xe2x88x924, xe2x88x923, xe2x88x922, xe2x88x921, 0, 1, 2, 3, 4}. It is assumed that the four input bits in FIG. 2 have weights xe2x88x924, 2, 1, and 1, respectively, which can be thought of as a conventional 3-bit two""s complement number with an extra least-significant bit. A digital logic block, such as digital encoder 204, converts each input sample to a unity weighted 8-bit number representation in which the value of each bit is taken to be xc2xd when the bit is high and xe2x88x92xc2xd when the bit is low. The digital encoder 204 selects the 8 bits such that the sum of the resulting bit values is equal to x[n]. For example, if x[n]=2, the digital encoder sets six of the bits labeled xi[n] in FIG. 2 high, and the remaining two bits low. It can be verified that if each one-bit DAC performs ideal zero-order-hold interpolation with an output value of xcex94/2 when the input bit is high and xe2x88x92xcex94/2 when the input bit is low, then the overall DAC is an ideal zero-order-hold DAC with an output that ranges from xe2x88x924xcex94 to 4xcex94 in steps of xcex94. Alternatively, if x[n] is restricted to the range {0, 1, . . . , 8}, the digital encoder sets x[n] of its output bits high and the rest of its output bits low, and the two possible output levels of each one-bit DAC are 0 and xcex94, then the overall DAC has an output that ranges from 0 to 8xcex94 in steps of xcex94.
In such composite DACs, e.g. composite DAC 200, the two sources of nonlinear distortion in the transient error are the one-bit DACs 2021-2028 and the analog summing operation 206. Although the summing operation 206 does introduce nonlinear distortion, such distortion can be minimized through the use of one-bit DACs with current-mode (i.e., high impedance) outputs such that the outputs can be summed by connecting them all to a low impedance load or a low impedance amplifier input. Therefore, in the following it is assumed that the summing operation does not introduce significant nonlinear distortion.
Further, it is assumed that the following two conditions hold for the composite DAC 200: 1) if presented with equivalent input all of the one-bit DACs 2021-2028 would introduce identical transient pulses, and 2) the transient pulse introduced by each one-bit DAC 2021-2028 in a given sample interval does not depend on the one-bit DAC""s input values during past or future sample intervals. In other words, suppose that the nth transient pulse introduced by each one-bit DAC 2021-2028 is ph(txe2x88x92nT) if the DAC input bit is high or pl(txe2x88x92nT) if the DAC input bit is low, where ph(t) and pl(t) are arbitrary but are common to all the one-bit DACs. For the composite DAC 200 with an arbitrary number, say N, of one-bit DACs, at the nth sample time x[n] of the one-bit DACs have their input bits set high and Nxe2x88x92x[n] have their input bits set low. Therefore, it follows from the original transient error equation (2) and the two conditions above that the transient error is given by:                                           e            t                    ⁡                      (            t            )                          =                                            ∑                              n                =                                  -                  ∞                                            ∞                        ⁢                          xe2x80x83                        ⁢                                          Np                l                            ⁡                              (                                  t                  -                  nT                                )                                              +                                                    x                ⁡                                  [                  n                  ]                                            ⁡                              [                                                                            p                      h                                        ⁡                                          (                                              t                        -                        nT                                            )                                                        -                                                            p                      l                                        ⁡                                          (                                              t                        -                        nT                                            )                                                                      ]                                      .                                              (        3        )            
The functions ph(t) and pl(t) do not depend on x[n], so this equation (3) indicates that the transient error is linearly related to x[n]; only linear distortion is introduced. Therefore, the two conditions stated above are sufficient to avoid nonlinear distortion in the transient error.
Known circuit layout and dynamic element matching techniques can be used to achieve the first of these conditions to a high degree of accuracy. However, it can be verified that the second condition is violated if one-bit DACs that approximate zero-order-hold interpolation are used.
The first prior art technique that avoids this problem uses one-bit DACs that implement an alternate type of interpolation known as return-to-zero (RTZ) interpolation. The idea behind RTZ interpolation is to perform zero-order-hold interpolation, or an approximation thereof, for only a portion (typically half) of each sample period, and to zero the output for the remainder of the sample period. In this way, the output of each one-bit DAC starts from zero at the beginning of every sample period, thereby eliminating the dependence of the transient pulses on previous one-bit DAC input values.
FIG. 3 provides a comparison between idealized and practical output waveforms for a one-bit DAC example that illustrates a practical (i.e., physically realizable) approximation to RTZ interpolation. More particularly, FIG. 3 is a signal diagram showing representative continuous-time output waveforms from a one-bit digital to analog converter (DAC) with ideal zero-order-hold interpolation (top waveform 300), from a practical one-bit DAC utilizing return to zero (RTZ) interpolation (middle waveform 302), and the transient error associated with the practical one-bit RTZ DAC (bottom waveform 304). The top plot 300 shows the output of a one-bit DAC with ideal zero-order-hold interpolation as a reference, and the middle plot 302 shows the corresponding practical version of RTZ interpolation. As is evident in FIG. 3, the RTZ output 302 approximates zero-order-hold interpolation for the first half of each sample interval and then settles to zero for the remainder of the sample interval. The bottom plot 304 shows the transient error which is the difference between the top and middle plots 300 and 302, respectively. Each transient pulse now consists of two components: the first component peaks at the start of the sample interval and settles to zero, and the second component starts half way through and persists to the end of the sample interval. Nevertheless, as is evident from FIG. 3 and which tends to be true in general, the transient pulse in a given sample interval is not a function of previous or future one-bit DAC input samples. Therefore, the second condition above is satisfied by one-bit DACs that implement practical RTZ interpolation.
In summary, the first prior art technique limits nonlinear distortion in the transient error introduced by composite DACs of the type shown in FIG. 2 through the use of current mode one-bit DACs that implement practical RTZ interpolation in conjunction with known circuit layout and dynamic element matching techniques to promote good matching among the one-bit DACs. In the following, the first prior art technique is referred to as the basic RTZ technique.
Unfortunately, the basic RTZ technique has three drawbacks. The first drawback is that nonlinear distortion is reduced relative to DACs that perform zero-order-hold interpolation at the expense of significantly increased linear distortion. As mentioned above, RTZ interpolation gives rise to a second component in each transient pulse. As illustrated in FIG. 3, this component occupies half of the sample interval and has a peak magnitude equal to that of the one-bit DAC output waveform, i.e., xcex94/2. Therefore, the power of the resulting transient error in the overall DAC output is comparable to that of the desired signal component. As explained above, the error is linear distortion which is generally preferable to nonlinear distortion. Nevertheless, it is still error and can be problematic in many applications, especially at such a high power level relative to the de sired signal component. The second drawback is that only half of each sample period is used by the one-bit DACs to generate the signal component of the overall DAC. To avoid introducing nonlinear distortion, each one-bit DAC must fully settle to zero in the second half of each sample period. Consequently, the approach requires one-bit DAC circuitry with approximately twice the speed of what would be necessary if the whole sample interval could be used for the settling process. The third drawback is that an additional timing signal is required to cause the one-bit DACs to begin the return-to-zero process half way through each sample interval. Most often, this necessitates a clock signal at twice the sample frequency.
The second prior art technique avoids the first drawback mentioned above. It is based on the idea of implementing each one-bit DAC as a pair of interleaved one-bit RTZ sub-DACs. Hence, it is referred to as the dual-RTZ technique. Representative waveforms are shown in FIG. 4 for the same one-bit DAC input sequence as in the basic RTZ example shown in FIG. 3.
FIG. 4 is a signal diagram showing representative continuous-time output waveforms from a pair of first and second interleaved RTZ sub-DACs utilizing a dual RTZ technique (top and middle waveforms, 400 and 402, respectively) and their sum (bottom waveform 404). The top plot 400 represents the output waveform of a first RTZ sub-DAC, and the middle plot 402 represents the output waveform of a second RTZ sub-DAC. The bottom plot 404 is the output of the dual-RTZ one-bit DAC obtained by summing the two outputs from the RTZ sub-DACs. Each RTZ sub-DAC in isolation is equivalent to a one-bit DAC in the basic RTZ technique described above, so its output contains only linear distortion. Therefore, there only can be linear distortion in the dual-RTZ one-bit DAC output (e.g., the bottom plot 404), because it is the sum of the two RTZ sub-DAC outputs. Consequently, the dual-RTZ technique offers the same advantage with respect to limiting nonlinear distortion as does the basic RTZ technique. However, the amount of linear distortion introduced by the dual-RTZ technique in the overall DAC output is greatly reduced relative to that of the basic RTZ technique, because each RTZ sub-DAC tends to cancel the large second transient pulse component of the other RTZ sub-DAC. As a result, the dual-RTZ one-bit DAC output waveform, e.g., the bottom plot 404, is a much better approximation to ideal zero-order-hold interpolation than the outputs of either of the RTZ sub-DACs in isolation.
Therefore, like the basic RTZ technique, the dual-RTZ technique limits nonlinear distortion in the transient error from composite DACs of the type shown in FIG. 2. However, unlike the basic RTZ technique, it does not introduce excessive linear distortion in the transient error, so it avoids the first drawback of the basic RTZ technique described above. Nevertheless, it is subject to the second two basic RTZ technique drawbacks described above: each RTZ sub-DAC in the dual-RTZ technique has the same settling requirements as in the basic RTZ technique and a timing signal is necessary to trigger the on and off portions of each RTZ sub-DAC.
The invention is briefly summarized by the claims that follow below. This invention relates generally to methods and apparatuses for implementing cyclic return to zero techniques for digital to analog conversion. Embodiments of the invention provide the benefits achieved by the basic RTZ and dual-RTZ techniques, discussed previously, with respect to limiting nonlinear distortion in the transient error, but are not subject to the previously discussed drawbacks associated with these techniques. Generally, embodiments of the invention disclose techniques for generating low-distortion continuous-time output waveforms in digital-to-analog converters (DACs) wherein the transient errors are not correlated with the DAC input signal, thereby resulting in DACs with significantly reduced nonlinear distortion.
In one embodiment, the invention discloses a method for performing cyclic return to zero (CRTZ) digital to analog conversion by generating at least two RTZ signals for performing digital to analog conversion. The method cycles between two RTZ signal generating circuits such that one of the RTZ signal generating circuits is active (i.e., converts a digital input bit into analog form) over at least an entire sample period generating an active signal (i.e., has not returned or is not returning to zero) while the other RTZ signal generating circuit returns to approximately zero or other approximately constant value (i.e., it becomes inactive) for the entire sample period. During the next period, the cycling occurs between the two RTZ signal generating circuits such that the RTZ signal generating circuit that was active during the previous sample period now returns to approximately zero or other approximately constant value and the other RTZ signal generating circuit that returned to approximately zero or other approximately constant value during the previous sample period becomes active. In contrast to the dual-RTZ technique, the RTZ waveforms in this method are not simply shifted versions of each other.
In other embodiments of the invention, a cyclic return to zero (CRTZ) digital to analog converter (DAC) includes at least two RTZ signal generating circuits, e.g. RTZ sub-DACs, to perform digital to analog conversion and a cycler, e.g. an RTZ sub-DAC cycler, to cycle between the two RTZ sub-DACs. The RTZ sub-DAC cycler cycles between the two RTZ sub-DACs such that one of the RTZ sub-DACs performs digital to analog conversion for an entire sample period while the other RTZ sub-DAC returns to approximately zero or other approximately constant value for the entire sample period. During the next period, the RTZ sub-DAC cycler switches between the two RTZ sub-DACs such that the RTZ sub-DAC that performed the digital to analog conversion during the previous sample period returns to approximately zero or other approximately constant value and the other RTZ sub-DAC that returned to zero or other approximately constant value during the previous sample period performs the digital analog conversion. In this fashion, each RTZ sub-DAC starts from approximately zero or an approximately constant value when converting an input bit to analog form and utilizes an entire sample period (in contrast to the dual-RTZ technique in which the RTZ sub-DACs zero their outputs part way through each sample period).
In further embodiments of the invention, at least three RTZ sub-DACs are utilized in either a random or a multi-period fashion. For example, a random RTZ sub-DAC cycler can be used to cycle between three RTZ sub-DACs in a random fashion. In yet another embodiment, a multi-period RTZ sub-DAC cycler can be used to cycle between three RTZ sub-DACs such that each RTZ sub-DAC holds its output value for at least two sample periods before returning to approximately zero or other approximately constant value. These and other embodiments will be discussed in further detail later.
Other features and advantages of the present invention will be set forth in part in the description which follows and the accompanying drawings, wherein the preferred embodiments of the present invention are described and shown, and in part will become apparent to those skilled in art upon examination of the following detailed description taken in conjunction with the accompanying drawings, or may be learned by the practice of the present invention. The advantages of the present invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.